1. Field of the Invention
The present invention relates generally to the field of buffering and latching of data input to high-speed digital circuits and systems, and more particularly, to a latched receiver circuit enabling simultaneous receipt of clock and data signals without any delay or buffering of the data or clock signal.
2. Discussion of the Prior Art
The transfer of data between integrated circuits such as high-speed digital circuits may be broken down to a timing budget in the overall system architecture. When data is received by an integrated circuit, it is typically buffered and latched and only after buffering and latching is the data considered successfully captured. In high speed digital circuits, the faster the data can be latched, the faster or, in some cases, the further data can be transmitted.
During digital circuit input operations, data enters the integrated circuit through an off-chip receiver and the data signal is buffered and fed to a latch. Typically, the data is captured by the latch on an edge or level of a system clock. To optimize this process, various input circuit implementations have been devised to minimize the delay through the buffer and setup time of the latch. For example, design and placement of input buffer and latch circuit components may minimize this time, but, currently result in some portion of the overall timing budget.
Various high-speed input latch/receiver devices having "low" set-up times may be found in U.S. Pat. No. 4,808,840 (edge-triggered latch), U.S. Pat. No. 5,097,157 (bus-receiver), U.S. Pat. Nos. 5,107,153, 5,117,124 (high-speed input receiver latch), U.S. Pat. Nos. 5,654,653, and 5,663,669 (several-stage latch). Representative of these patent disclosures is U.S. Pat. No. 5,107,153 which describes a latch circuit that delays the signals to control setup time.
The ideal situation is to have zero delay through the input buffer and zero setup time for the latch. This results in a zero timing penalty for the data path if this is achieved without delaying the clock or data. For high speed digital I/O, the problem is further complicated due to the signal swing of the incoming signals. High performance I/O device technologies such as GTL or HSTL have voltage swings smaller than the IC's native voltage. This requires the input receiver to amplify the incoming signal before it is captured by the latch, adding further delay to the timing penalty. Above-mentioned U.S. Pat. No. 5,654,653 describes a system bus receiver of reduced set-up time by latching unamplified bus voltage.
It would be highly desirable to provide a latched-receiver circuit with a zero setup time, i.e., capable of receiving data and clock signals simultaneously without amplification of the data signal or clock signal delay.